* Copyright: SiCED Electronics Development GmbH & Co. KG
* ****************************************************************
* Models provided by SiCED are not warranted by SiCED as
* fully representing all of the specifications and operating
* characteristics of the semiconductor product to which the
* model relates. The model describe the characteristics of a
* typical device.
* In all cases, the current data sheet information for a given
* device is the final design guideline and the only actual
* performance garantee.
* Altough models can be a useful tool in evaluating device
* performance, they cannot model exact device performance under
* all conditions, nor are they intended to replace bread-
* boarding for final verification. SiCED reserves the right
* to change models without prior notice.
* ****************************************************************
* version v1a (July 2009)
* model based on measured data (temperature range -40°C - 225°C)
* of a typical 1200V JFET mounted in TO220
********************************************************************
* content:
* JFET_INF06_1200V_L1
* JFET_INF06_1200V_L3
* JFET_INF06_1200V_L3b
* *******************************************************************
* Example:
 *XJFET	Drain Gate Source	                              JFET_INF06_1200V_L1
* XJFET    Drain Gate Source	Tj  TCase	              JFET_INF06_1200V_L3  LossSwitch=1
* XJFET    Drain Gate Source	Tj  TAmb  TCase   JFET_INF06_1200V_L3b  LossSwitch=1
* LossSwitch = 0	-> dissipated power  = 0 (default value, can be omitted)
* LossSwitch <> 0	-> dissipated power  = Current_JFET x Voltage_JFET
*
* Further Parameters and the default values: Ls=1n Ld=1n Lg=5n Rg=6 Vpi=17 dVpp=8 SCIS=1 Ron=110
* Ls, Ld, Lg: Source, Drain, and Gate Inductance in Henry
* Rg: Internal Gate Resistance in Ohm
* Vpi: Pinch Off Voltage (absolute value)
* dVpp: Difference (Breakdown voltage of Gate-Source diode) - (Pinch Off Voltage)
* SCIS: Scaling factor for saturation current
* Ron: On-Resistance in mOhm
* Limits: 10V <= Vpi <= 25V, 7V <= dVpp <= 9V, 0.5 <= SCIS <= 1.5, 80mOhm <= Ron <= 160mOhm
*****************************************************************
* thermal nodes of level 3 model:
*
*  JFET_INF06_1200V_L3 :
*  Tj :    potential(in V) = temperature (in °C) at junction (monitor node,  typically not connected)                                       
*  Tcase : node where the boundary condition - external heat
*          sinks etc - have to be connected (ideal heat sink
*          can be modeled by using a voltage source stating the
*          ambient temperature in °C between Tcase and ground.
*
*  JFET_INF06_1200V_L3b :
*  Equivalent to L3, usage of thermal nodes TCase and Tamb as in the previous model JFET_Mod_D41_V1.1C
***************************************************************************************************************************************************


.SUBCKT JFET_INF06_1200 D G S Tj PARAMS: LossSwitch=0 Vpi=17 dVpp=8 SCIS=1 Ron=110

.PARAM V_pi={limit(Vpi,10,25)}
.PARAM dV_pp={limit(dVpp,7,9)}
.PARAM SC_IS={limit(SCIS,0.5,1.5)}
.PARAM R_on={limit(Ron,80,160)}

.PARAM SC_KR={SC_IS*R_on/110}
.PARAM sv3={17/V_pi}
.PARAM sv1={sv3*sv3}
.PARAM sv2={sv3*sv3*sv3}

.PARAM  ISP1A = {0.2677*sv1}      ISP1B = {4.456E-4*sv1}  ISP1C ={-5.698E-6*sv1}  ISP1D = {9.929E-9*sv1}
.PARAM  ISP2A ={-2.644E-3*sv2}  ISP2B ={-1.163E-5*sv2}  ISP2C = {1.154E-7*sv2}  ISP2D ={-1.359E-10*sv2}
.PARAM   ISP3A = {-17/sv3}          ISP3B = 0

.PARAM  KRP1A = {0.01575*sv1}   KRP1B = {3.383E-5*sv1}
.PARAM  KRP2A ={-1.316E-4*sv2}  KRP2B = {6.353E-7*sv2}  KRP2C = {6.549E-9*sv2}
.PARAM 	KRP3A = {-20/sv3}    KRP3B = 0

.PARAM  f2=1563p   f1a=25.07p          f1b=4499p         f1c=189.2p        f1d=58.25p   f3=1660p  ps9=6.22
.PARAM  U0=2.9    ps2={-1/3.858}      ps3={-1/26.95}   ps4={-1/271.9} 

.PARAM Cmax={f1b*exp(ps2*ps9)}
.PARAM ps10={f1b/(ps2*Cmax)}

.PARAM  Cds0={f2}
.PARAM  Cox1={f1a}
.PARAM  Cox2={Cmax}
.PARAM  Cox3={f1c}
.PARAM  Cox4={f1d}
.PARAM  Cgs={f3}

.FUNC KRP1(T)	{ KRP1A + KRP1B*T }
.FUNC KRP2(T)	{ KRP2A + KRP2B*T + KRP2C*T*T}
.FUNC KRP3(T)	{ KRP3A + KRP3B*T }
.FUNC ISP1(T)	{ ISP1A + ISP1B*T + ISP1C*T*T + ISP1D*T*T*T }
.FUNC ISP2(T)	{ ISP2A + ISP2B*T + ISP2C*T*T + ISP2D*T*T*T}
.FUNC ISP3(T)	{ ISP3A + ISP3B*T }
.FUNC KR(T,VG)	{ SC_KR*((KRP1(T)*(VG-KRP3(T))*(VG-KRP3(T)))+(KRP2(T)*(VG-KRP3(T))*(VG-KRP3(T))*(VG-KRP3(T)))) }
.FUNC IS(T,VG)	{ SC_IS*((ISP1(T)*(VG-ISP3(T))*(VG-ISP3(T)))+(ISP2(T)*(VG-ISP3(T))*(VG-ISP3(T))*(VG-ISP3(T)))) }
.FUNC ID(T,VG,VD)	{IF( VG>ISP3A,(VD/abs(VD))*IS(T,VG)*(1-exp(-abs(VD)/KR(T,VG))),1e-9 ) }

*JFET current
GIDK	d	s0	VALUE = {ID(V(Tj,0),V(g,s),V(d,s))}
Vcurr	s0	s  DC=0

E_Eds     d edep  VALUE {(V(d,s)-2*(SQRT(U0*(limit(U0+V(d,s),0,2000)))-U0))}
C_Cds  edep    s  {Cds0}

Vx        d   ox1 0
C_Cdg1  ox1   g   {Cox1}
E_Edg2    d   ox2 VALUE 
+  {if(V(d,g)>ps9,V(d,g)-(ps10*(exp(ps2*V(d,g))-exp(ps2*min(V(d,g),ps9)))+min(V(d,g),ps9)),0)}
C_Cdg2   ox2   g   {Cox2}
E_Edg3    d   ox3 VALUE {if(V(d,g)>0,V(d,g)-(exp(ps3*max(V(d,g),0))-1)/ps3,0)}
C_Cdg3  ox3   g   {Cox3}
E_Edg4    d   ox4 VALUE {if(V(d,g)>0,V(d,g)-(exp(ps4*max(V(d,g),0))-1)/ps4,0)}
C_Cdg4  ox4   g   {Cox4}

Cgs   g s {Cgs}

*gate diodes
DA	g	g1	DGF
DB	s	g1	DGS
RGS	g	s	1.7E8
.model	DGF	D	(LEVEL=1 BV={V_pi+dV_pp}  RS=0.05)
.model	DGS	D	(LEVEL=1 BV=1.44 RS=70)

*reverse diode (vers. v1.1d)
D1  s0 mid FWDBL1
D2  s0 mid FWDBL2
.MODEL FWDBL1 D RS=0.0	BV=10000
.MODEL FWDBL2 D RS=60k	BV=1300

.PARAM	RWDA = 1.15
.PARAM	RWDB = 2.87
EDIO1	mid	miv1	VALUE = {IF(V(s0,mi) > RWDA, RWDA+sqrt(I(VID0)/RWDB)-0.90, 0)}
EDIO2	miv1	miv2	VALUE = {IF(V(s0,mi) <= RWDA, IF(V(s0,mi) > 0, I(VID0)*1e9, 0), 0)}
VID0	miv2	mi	0
VITOT	mi	d	0

*thermal
G_TH  0   Tj   VALUE={ LIMIT(IF(LossSwitch==0,0,abs(I(Vcurr)*(V(d,s))) ),0,1e6)}

.ENDS

*****************************************************************************************************

.SUBCKT JFET_INF06_1200V_L1 drain gate source PARAMS: Ls=1n Ld=1n Lg=5n Rg=6
+             Vpi=17 dVpp=8 SCIS=1 Ron=110

.PARAM   dgfs=0

X1  d g s Tj JFET_INF06_1200 PARAMS: Vpi={Vpi} dVpp={dVpp} SCIS={SCIS} Ron={Ron}

Rg    g1     g    {Rg} 
  
Lg    gate   g1  {Lg*if(dgfs==99,0,1)}
Ls    source s   {Ls*if(dgfs==99,0,1)}
Ld    drain  d   {Ld*if(dgfs==99,0,1)}

E1    Tj     w      VALUE={TEMP}
R1    w      0      1u

.ENDS

****************************************************************************************************

.SUBCKT JFET_INF06_1200V_L3 drain gate source Tj Tcase PARAMS: Ls=1n Ld=1n Lg=5n Rg=6 LossSwitch=0
+             Vpi=17 dVpp=8 SCIS=1 Ron=110

.PARAM   dgfs=0

X1  d g s Tj JFET_INF06_1200 PARAMS: LossSwitch={LossSwitch} Vpi={Vpi} dVpp={dVpp} SCIS={SCIS} Ron={Ron}

Rg    g1     g    {Rg} 
  
Lg    gate   g1  {Lg*if(dgfs==99,0,1)}
Ls    source s   {Ls*if(dgfs==99,0,1)}
Ld    drain  d   {Ld*if(dgfs==99,0,1)}

RTH1	Tj	TH1	0.05935
RTH2	TH1	TH2	0.08134
RTH3	TH2	TH3	0.10603
RTH4	TH3	TCase	0.03969
CTH1	Tj	0	0.00789
CTH2	TH1	0	0.00769
CTH3	TH2	0	0.07607
CTH4	TH3	0	1.56923
CTH5	TCase	0	1.56923

.ENDS

****************************************************************************************************

.SUBCKT JFET_INF06_1200V_L3b drain gate source Tj Tamb Tcase PARAMS: Ls=1n Ld=1n Lg=5n Rg=6 LossSwitch=0
+             Vpi=17 dVpp=8 SCIS=1 Ron=110

.PARAM   dgfs=0

X1  d g s Tj JFET_INF06_1200 PARAMS: LossSwitch={LossSwitch} Vpi={Vpi} dVpp={dVpp} SCIS={SCIS} Ron={Ron}

Rg    g1     g    {Rg} 
  
Lg    gate   g1  {Lg*if(dgfs==99,0,1)}
Ls    source s   {Ls*if(dgfs==99,0,1)}
Ld    drain  d   {Ld*if(dgfs==99,0,1)}

RTH1	Tj	TH1	0.05935
RTH2	TH1	TH2	0.08134
RTH3	TH2	TH3	0.10603
RTH4	TH3	TCase	0.03969
CTH1	Tj	0	0.00789
CTH2	TH1	0	0.00769
CTH3	TH2	0	0.07607
CTH4	TH3	0	1.56923

.ENDS