* * Copyright: SiCED GmbH&Co.KG * **************************************************************** * Models provided by SiCED are not warranted by SiCED as * fully representing all of the specifications and operating * characteristics of the semiconductor product to which the * model relates. The model describe the characteristics of a * typical device. * In all cases, the current data sheet information for a given * device is the final design guideline and the only actual * performance garantee. * Altough models can be a useful tool in evaluating device * performance, they cannot model exact device performance under * all conditions, nor are they intended to replace bread- * boarding for final verification. SiCED reserves the right * to change models without prior notice. * * **************************************************************** * version v2b (Feb 2009) * model based on measured data (temperature range 25°C-250°C) * of a typical 1200V JFET mounted in TO220 * ******************************************************************** * content: * JFET_INF04_1200V_L1 * JFET_INF04_1200V_L3 * JFET_INF04_1200V_L3b * ******************************************************************* * Example: *XJFET Drain Gate Source JFET_INF04_1200V_L1 * XJFET Drain Gate Source Tj TCase JFET_INF04_1200V_L3 LossSwitch=1 * XJFET Drain Gate Source Tj TAmb TCase JFET_INF04_1200V_L3b LossSwitch=1 * LossSwitch = 0 -> dissipated power = 0 (default value, can be omitted) * LossSwitch <> 0 -> dissipated power = Current_JFET x Voltage_JFET * Further Parameters and the default values: Ls=1n Ld=1n Lg=5n Rg=2 * ***************************************************************** * thermal nodes of level 3 model: * * JFET_INF04_1200V_L3 : * Tj : potential(in V) = temperature (in °C) at junction (monitor node, typically not connected) * Tcase : node where the boundary contition - external heat * sinks etc - have to be connected (ideal heat sink * can be modeled by using a voltage source stating the * ambient temperature in °C between Tcase and ground. * * JFET_INF04_1200V_L3b : * Equivalent to L3, usage of thermal nodes TCase and Tamb as in the previos model JFET_Mod_D41_V1.1C * * ************************************************************************************************************************************************* .SUBCKT JFET_1200 D G S Tj PARAMS: LossSwitch=0 .PARAM ISP1A = 9.5038E-2 ISP1B = -2.1720E-4 ISP2A = -2.0088E-3 ISP2B = 6.5673E-6 .PARAM ISP3A = -1.9000E1 ISP3B = 0 KRP1A = 5.1770E-2 KRP1B = 9.4692E-5 .PARAM KRP2A = -1.6794E-3 KRP2B = -2.4340E-7 KRP3A = -1.9000E1 KRP3B = 0 .PARAM f2=440p f1a=17.49p f1b=1500p f1c=769.5p f1d=44.27p f3=610p ps9=4 .PARAM U0=2.9 ps2={-1/2.5} ps3={-1/12.32} ps4={-1/193.3} .PARAM Cmax={f1b*exp(ps2*ps9)} .PARAM ps10={f1b/(ps2*Cmax)} * .PARAM Cds0={f2} .PARAM Cox1={f1a} .PARAM Cox2={Cmax} .PARAM Cox3={f1c} .PARAM Cox4={f1d} .PARAM Cgs={f3} .FUNC KRP1(T) { KRP1A + KRP1B*T } .FUNC KRP2(T) { KRP2A + KRP2B*T } .FUNC KRP3(T) { KRP3A + KRP3B*T } .FUNC ISP1(T) { ISP1A + ISP1B*T } .FUNC ISP2(T) { ISP2A + ISP2B*T } .FUNC ISP3(T) { ISP3A + ISP3B*T } .FUNC KR(T,VG) { (KRP1(T)*(VG-KRP3(T))*(VG-KRP3(T)))+(KRP2(T)*(VG-KRP3(T))*(VG-KRP3(T))*(VG-KRP3(T))) } .FUNC IS(T,VG) { (ISP1(T)*(VG-ISP3(T))*(VG-ISP3(T)))+(ISP2(T)*(VG-ISP3(T))*(VG-ISP3(T))*(VG-ISP3(T))) } .FUNC ID(T,VG,VD) {IF( VG>ISP3A,(VD/abs(VD))*IS(T,VG)*(1-exp(-abs(VD)/KR(T,VG))),1e-9 ) } *JFET current GIDK d s0 VALUE = {ID(V(Tj,0),V(g,s),V(d,s))} Vcurr s0 s DC=0 *gate diodes DA g g1 DGF DB s g1 DGS RGS g s 5.65E8 .model DGF D (LEVEL=1 BV=28 RS=0.05) .model DGS D (LEVEL=1 BV=1.44 RS=70) E_Eds d edep VALUE {(V(d,s)-2*(SQRT(U0*(limit(U0+V(d,s),0,2000)))-U0))} C_Cds edep s {Cds0} Vx d ox1 0 C_Cdg1 ox1 g {Cox1} E_Edg2 d ox2 VALUE + {if(V(d,g)>ps9,V(d,g)-(ps10*(exp(ps2*V(d,g))-exp(ps2*min(V(d,g),ps9)))+min(V(d,g),ps9)),0)} C_Cdg2 ox2 g {Cox2} E_Edg3 d ox3 VALUE {if(V(d,g)>0,V(d,g)-(exp(ps3*max(V(d,g),0))-1)/ps3,0)} C_Cdg3 ox3 g {Cox3} E_Edg4 d ox4 VALUE {if(V(d,g)>0,V(d,g)-(exp(ps4*max(V(d,g),0))-1)/ps4,0)} C_Cdg4 ox4 g {Cox4} Cgs g s {Cgs} *reverse diode (vers. v1.1d) D1 s0 mid FWDBL1 D2 s0 mid FWDBL2 .MODEL FWDBL1 D RS=0.0 BV=10000 .MODEL FWDBL2 D RS=60k BV=1120 .PARAM RWDA = 1.086 .PARAM RWDB = 0.453 EDIO1 mid miv1 VALUE = {IF(V(s0,mi) > RWDA, RWDA+sqrt(I(VID0)/RWDB)-0.90, 0)} EDIO2 miv1 miv2 VALUE = {IF(V(s0,mi) <= RWDA, IF(V(s0,mi) > 0, I(VID0)*1e9, 0), 0)} VID0 miv2 mi 0 VITOT mi d 0 *thermal G_TH 0 Tj VALUE={ LIMIT(IF(LossSwitch==0,0,abs(I(Vcurr)*(V(d,s))) ),0,1e6)} .ENDS ***************************************************************************************************** .SUBCKT JFET_INF04_1200V_L1 drain gate source PARAMS: Ls=1n Ld=1n Lg=5n Rg=2 .PARAM dgfs=0 X1 d g s Tj JFET_1200 Rg g1 g {Rg} Lg gate g1 {Lg*if(dgfs==99,0,1)} Ls source s {Ls*if(dgfs==99,0,1)} Ld drain d {Ld*if(dgfs==99,0,1)} E1 Tj w VALUE={TEMP} R1 w 0 1u .ENDS **************************************************************************************************** .SUBCKT JFET_INF04_1200V_L3 drain gate source Tj Tcase PARAMS: Ls=1n Ld=1n Lg=5n Rg=2 LossSwitch=0 .PARAM dgfs=0 X1 d g s Tj JFET_1200 PARAMS: LossSwitch={LossSwitch} Rg g1 g {Rg} Lg gate g1 {Lg*if(dgfs==99,0,1)} Ls source s {Ls*if(dgfs==99,0,1)} Ld drain d {Ld*if(dgfs==99,0,1)} RTH1 Tj TH1 0.217 RTH2 TH1 TH2 0.430 RTH3 TH2 TH3 0.267 RTH4 TH3 TCase 0.154 CTH1 Tj 0 0.00052 CTH2 TH1 0 0.0042 CTH3 TH2 0 0.029 CTH4 TH3 0 0.239 CTH5 TCase 0 0.239 .ENDS **************************************************************************************************** .SUBCKT JFET_INF04_1200V_L3b drain gate source Tj Tamb Tcase PARAMS: Ls=1n Ld=1n Lg=5n Rg=2 LossSwitch=0 .PARAM dgfs=0 X1 d g s Tj JFET_1200 PARAMS: LossSwitch={LossSwitch} Rg g1 g {Rg} Lg gate g1 {Lg*if(dgfs==99,0,1)} Ls source s {Ls*if(dgfs==99,0,1)} Ld drain d {Ld*if(dgfs==99,0,1)} RTH1 Tj TH1 0.217 RTH2 TH1 TH2 0.430 RTH3 TH2 TH3 0.267 RTH4 TH3 TCase 0.154 CTH1 Tj Tamb 0.00052 CTH2 TH1 Tamb 0.0042 CTH3 TH2 Tamb 0.029 CTH4 TH3 Tamb 0.239 .ENDS